e2v, the leading designer, developer and manufacturer of specialised components and subsystems, has announced the selection of the CORTUS APS3 CPU core for sensor interface mixed signal ASICs, fulfilling e2v’s exacting system-on-a-chip requirements in terms of high performance, size, and power processing.
e2v''''s Mixed Signal ASIC (MSA) business unit specialises in providing customised solutions for sensor data acquisition for automotive, medical and industrial markets, specifically in safety and security, energy management, pollution reduction, health and sport applications.
e2v’s approach to designing mixed signal ASICs has been to deliver more intelligence on the chip by embedding increased processing performance, and focusing on reducing unit cost and power consumption.
“In the mixed signal IC domain, power and cycle efficiency are even more critical than in full digital SOCs with their very high gate counts. This is why e2v has selected the CORTUS APS3 32-bit CPU core for mixed signal ASICs, or ASSPs”, said Franck Berny, marketing and applications manager at e2v''''s MSA business unit.
The efficiency of the APS3’s instruction set, and associated tool chain, allow much denser code, requiring a significantly smaller code memory area. Increased code density also leads to fewer clock cycles and hence a lower power requirement and less noise. Equally, in terms of efficiency, the 32-bit architecture is well suited for high dynamic range calculations such as those typically performed in sensor applications. The coprocessor interface and software tool support, comprising advanced GNU based compilers and debuggers, including the Integrated Development Environment (IDE) “Eclipse” framework, allow further optimisation through the integration of hardware accelerators.
e2v recently announced the availability of its new Mixed Signal ASIC Development Kit, CAPRI2, a leading edge toolset for pre-developing and validating entire sensing systems and improving new product time-to-market. This great plug-and-play tool for e2v’s customers comprises several daughter boards each containing an analogue front-end specific to a particular sensing element (resistive, capacitive etc.), and a shared mother board representative of the future ASIC digital partition, which can embed the APS3’s small footprint 32-bit CPU within an FPGA .
This Development Kit approach gives e2v designs the full benefit of the ultra high performance APS3 CPU, associated to fast and first-silicon-right designs, thanks to proven silicon and reusable building blocks.
“With a silicon footprint as small as 8 bit cores, the 32 bit APS3 CPU gives e2v a twofold competitive advantage over legacy 8 bit cores traditionally used in sensor interface mixed signal ICs”, added Philippe Kuntz, embedded systems team manager at e2v.
Please contact your local e2v sales office for pricing and additional information.